Various issues arise in attempting to satisfy the ever increasing demands for microminiaturization, particularly in fabricating non-volatile semiconductor devices, such as flash memory devices, e.g., electrically erasable programmable read only memory (EEPROM) devices. The demands for continuing microminiaturization led to the fabrication of flash memory devices comprising transistors having a gate width of about 0.13 micron and under and gate structures spaced apart by a small gap of about 0.30 micron or less. In accordance with conventional practices, an oxide sidewall spacer is formed on side surfaces of the gate stack, and the first interlayer dielectric (ILD0) is deposited over the gate structures filling the gaps therebetween.
As microminiaturization proceeds apace, various reliability issues arise, particularly as EEPROM device dimensions are scaled into the deep sub-micron regime, such as UV charging during back end of line processing, such as deposition, metal etching and passivation, particularly during plasma processing. UV radiation generated during such processing results in undesirable UV charging of the flash memory devices with an attendant increase in threshold voltage (Vt). Cells which are subjected to UV charging and exhibit an increased Vt, are extremely difficult to over-program and also difficult to over-erase. If the initial Vt, is increased, there is less of a Vt window between the erased state and the programmed state, thereby causing various reliability and operating speed problems.
Accordingly, there exists a need for microminiaturized semiconductor devices, such as flash memory devices, e.g., EEPROMS, with improved reliability and increased operating speed, and for efficient methodology enabling the fabrication of such devices with reduced UV cell charging.